Résumé
Name: Felix Wu 吴非
Date of Birth: June 1982
Location: Beijing, China
Email: xeroncn # hotmail
Phone: +86 l58OlOlO38O (WeChat)

Education
Nankai University, Department of Microelectronics
Master's in Microelectronics and Solid-State Electronics, Integrated Circuit Design (2006 - 2009)
Nankai University, Department of Microelectronics
Bachelor's in Microelectronics (1999 - 2003)

Self-Evaluation
I have some chip testing experience, some digital design experience, and extensive digital verification experience.
I am familiar with various verification methodologies and script development.
I have experience with fully digital chips and mixed-signal chips, having participated in projects for consumer electronics and industrial products.
There are still many unknown areas, and I am on a continuous learning path. I consider myself diligent and hardworking, striving to learn throughout my life.

Work Experience

2023 - Present, Beijing, Muye Microelectronics (牧野微电子), Senior Digital Verification Manager

    Established a UVM-based SoC simulation verification environment from scratch, participating in the integration of FPGA simulation and AMS mixed-signal simulation.
    Developed all simulation scripts, regression scripts, and register maintenance development scripts using Python.
    Developed and evaluated VIPs, maintained and developed other productivity tools.
    Evaluated FuSa-related EDA tools and verified functional safety mechanisms.
    Conducted recruitment interviews and built a verification team, managing team members across multiple sites.
    Managed and participated in Matlab modeling, module-level verification, and system-level verification for a vehicle millimeter-wave radar (MMIC) project.
    Participated in managing the design team and contributed to some digital module designs.

2022 - 2023, Beijing, Zvision Technology (一径科技), Senior Digital Verification Manager

    Established a UVM-based SoC simulation verification environment from scratch, and maintained FPGA simulation environment.
    Developed all simulation scripts, regression scripts, and register maintenance development scripts using Python.
    Developed and evaluated VIPs, evaluated EDA tools, maintained and managed the Git databases, and developed other productivity tools.
    Conducted recruitment interviews and built a local verification team, promoting verification methodologies to other departments such as algorithms and software.
    Managed and participated in module-level and system-level verification for a vehicle laser radar (Lidar) project.
    Contributed to some design work.

2015 - 2022, Beijing, Analog Devices Inc., Manager, Digital Verification Engineer

    Responsible for the design and integration of the audio subsystem in a digital audio processing chip project, as well as the initial SoC verification environment development for the project, supporting PC-side simulation of FPGA platform code.
    Established and was responsible for the operation, maintenance, and promotion of the IP database in the China division, guiding multinational team collaboration in IP design and verification.
    Participated as a verification lead in the development of multiple chips and IPs within the company, collaborating with multinational teams on products including energy metering, digital encryption/decryption algorithms (SHA, AES, etc.).
    Developed a platform based on C/C++ to accelerate the speed and efficiency of firmware verification for a DSP chip, which has been used in subsequent chip developments in that product series.
    Familiar with Palladium hardware accelerators and used them to improve verification work on certain projects with significant results.
    Experienced with formal verification tools like JasperGold and used them in multiple projects.
    Participated in various projects including optical communication, Battery management system (BMS), etc., covering module-level verification, system-level verification, post-simulation, and script development.
    Presented papers and speeches at the company's global and China technology conferences multiple times.
    Involved in recruitment interviews.

2014 - 2015, Beijing, Greenliant Systems (绿芯半导体系统科技), Lead, Staff Digital Verification Engineer

    Developed and maintained simulation verification scripts.
    Responsible for DMA module-level verification for several enterprise SSD controller chips, using UVM verification methodology.
    Verification lead for an SSD controller chip project.
    Participated in recruitment interviews.

2010 - 2014, Beijing, Vimicro Microelectronics (中星微电子), Senior Digital Verification Engineer

    Independently responsible for digital verification of the Ethernet subsystem for an AP chip and several sub-products, familiar with 10M/100M/1000M Ethernet protocols, with limited involvement in USB subsystem verification for the product.
    Participated in and was responsible for low-power verification of a chip project, publishing results at the Synopsys Users Group Conference (SNUG China).
    Participated in other projects including algorithm module verification (Noise Reduction, etc.) in an ISP chip, audio (I2S) protocol verification in a mixed-signal chip, and AMBA AXI bus functional and performance verification, covering module-level, system-level, and post-simulation.
    Developed a module-level verification environment (I2C) used in training courses for new employees.
    Used VMM verification methodology.

2009 - 2010, Beijing, Raycom Technology (润光泰力), Junior Digital Verification Engineer

    Conducted timing analysis for an FPGA project, primarily using Synplify.
    Responsible for module-level verification for an optical communication project, using OVM verification methodology.

2003 - 2006, Tianjin, TCMC Microelectronics (中晶微电子), IC Test Engineer

    Participated in testing of analog chips, including PCB design, functional and performance testing, etc.
    Participated in testing of other mixed-signal chips, developing FPGA test code.